(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating a pattern for conductive interconnects in a layer of photo-active dielectric material without using a separate layer of photoresist for the exposure and patterning of the layer of photo-active dielectric material.
(2) Description of the Prior Art
In the formation of semiconductor integrated circuits, it is common practice to form interconnect metal line structures on a number of different levels within the structure and interconnecting the various levels of wiring with contact or via openings.
The first or lowest level of interconnect wires is typically formed as a first step in the process after which a second or overlying level of interconnect wires is deposited over the first level.
The first level of interconnect wires is typically in contact with active regions in a semiconductor substrate but is not limited to such contact. The first level of interconnect can for instance also be in contact with a conductor that leads to other devices that form part of a larger, multi-chip structure. The two levels of metal wires are connected by openings between the two layers that are filled with metal where the openings between the two layers are lined up with and match contact points in one or both of the levels of metal lines.
Previously used techniques to form multi-levels of wiring apply the technique of first forming the interconnect level metal in a first plane followed by forming the overlying level of interconnect wire in a second plane. This structure typically starts with the surface of a semiconductor substrate into which active devices have been created.
The surface into which the pattern of interconnect lines of the first plane is formed may also be an insulation layer deposited over-the surface of the substrate or a layer of oxide may first have been formed on the surface of the substrate. After the layer, into which the pattern of interconnecting wires has to be created, has been defined, the interconnecting pattern itself needs to be defined. This is done using conventional photolithographic techniques whereby the openings are made (in the layer) above the points that need to be contacted in the substrate.
The openings, once created, may be lined with layers of material to enhance metal adhesion (to the sidewalls of the opening), the glue layer, or to prevent diffusion of materials into and from the substrate in subsequent processing steps, the barrier layer.
The final phase in creating the first level of interconnect lines is to fill the created openings with metal, typically aluminum, tungsten or copper, dependent on the particular application and the requirements and restrictions that are imposed by such parameters as line width, aspect ratio of the opening, required planarity of the surface of the deposited metal and others. This process of line formation in overlying layers of metal can be repeated in essentially the same manner as highlighted for the first layer of interconnecting wires.
Applying conventional methods of creating conductive interconnect patterns typically results in the consumption of large amounts of chemicals that are related to photolithographic exposure of the interconnect pattern and to the Reactive Ion Etching (RIE) process that is thereby applied. Due to this consumption of chemicals, the cost of creating conductive interconnect patterns continues to increase, more so in the era of new technology in which more stringent design requirements are imposed.
The increasing use of low-k dielectrics for the insulation of the conductive interconnects further presents additional challenges in the creation of conductive interconnects, such as the potential contamination of the low-k dielectric material during the removal of the exposed photoresist mask after the interconnect pattern has been transferred to the low-k dielectric. A further problem is presented by damage to the low-k dielectric as a result of long exposure times required as part of the applied RIE.
The invention addresses these concerns and provides for the use of a dielectric material into which an interconnect pattern can be directly exposed without the use of an overlying exposure photoresist mask.
U.S. Pat. No. 6,506,979 (Shelnut et al.), U.S. Pat. No. 5,334,488 (Shipley, Jr.) and U.S. Pat. No. 6,521,328 (Lauffer et al.) describe the use of photo-active dielectrics in printed circuit board manufacture.
U.S. Pat. No. 6,349,456 (Dunn et al.) teaches forming a resistor using a photo-active dielectric (PAD).